AERO: Design Space Exploration Framework for Resource-Constrained CNN Mapping on Tile-Based Accelerators
نویسندگان
چکیده
Analog In-Memory Compute (AIMC) arrays can store weights and perform matrix-vector multiplication operations for Deep Convolutional Neural Networks (CNNs). A number of recent efforts have integrated AIMC into hybrid digital-analog accelerators in a multi-layer parallel manner to achieve energy efficiency high throughput. Multi-layer parallelism on large-scale tile-based architectures need efficient mapping support at the processing element (PE)-level ( e.g. , digital or analog elements) tile-level. To find most architectures, fast accurate design space exploration (DSE) is required. In this paper, novel DSE framework, AERO, presented characterize CNN inference workload executing that supports parallelism. Three characteristics be seen our framework: (1) It presents hierarchical Tile/PE-level strategy including inter-layer interaction, allowing layer fusion/splitting configurations PE-level optimization. (2) unlocks different Performance, Power Area (PPA) points under both sufficient limited resource constraints, while case not considered prior works architectures. The impact weight loading stationary are analyzed better insights (3) incorporates detailed PPA model broad range units tile. Experimental case-studies performed realistic relevant benchmarks such as MLP, CNNs (Lenet-5, Resnet-18,-34,-50 −101).
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ژورنال
عنوان ژورنال: IEEE Journal on Emerging and Selected Topics in Circuits and Systems
سال: 2022
ISSN: ['2156-3365', '2156-3357']
DOI: https://doi.org/10.1109/jetcas.2022.3171826